FIG. 5 is a block diagram illustrating a structure of a prior art digital filter for 2D image processing. Referring now to the explanatory drawings, FIG. 4A illustrates a typical matrix-like image display and FIG. 4B illustrates an enlarged view of each picture element X11 through X33 of the 3.times.3 matrix shown within the large circle in FIG. 4A. The picture element data of each of the picture elements X11 through X33 is designated respectively as x11 through x33 (this designation will also be employed in the description of preferred embodiments of the invention).
FIG. 5 shows the circuit wherein a digital filtering process is carried out on the center picture element X22 in the 3.times.3 matrix in FIG. 4B. DLY 1 through DLY 6 denote delay circuits. Picture element data x12 and x11 are delayed respectively by 1 system clock cycle and 2 system clock cycles by the delay circuits DLY1 and DLY2, picture element data x22 and x21 are delayed respectively by 1 system clock cycle and 2 system clock cycles by the delay circuits DLY3 and DLY4 and picture element data x32 and x31 are delayed respectively by 1 system clock cycle and 2 system clock cycles by the delay circuits DLY5 and DLY6. Each of these picture element data x11 through x33 are multiplied by a coefficient that corresponds to the respective picture element by a respective multiplier MPY. An adder ADD adds each of the multiplication outputs and its addition output DOUT represents picture element data of the center picture element X22 after the digital filtering process.
Generally, the multiplier requires a large scale circuit. Consequently, the prior art example described above has a problem in that, since the multipliers MPY each require such a large scale circuit, and are required for each picture element X11 through X33, the size of the circuit of the whole system is large.